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Direct Memory Access Controller
• Ability of each stream to indicate a transfer error via an interrupt
• 16-word First-In, First Out (FIFO) array, with pack and unpack logic to handle all input/
output combinations of byte, half-word, and word transfers
• APB slave port for programming of its registers by the ARM core
• AHB port for data transfers.
12.2 DMA Theory Of Operation
One central DMA Controller services all DMA requirements for DMA-capable devices (see
Table 12-1 for a list of supported devices). The DMA is controlled by the system clock.
The DMA Controller transfers data between AHB peripherals and memory or between
memory and memory. The DMA Controller supports four data streams (Stream0, Stream1,
Stream2, and Stream3) that can be used to service:
• Four peripheral data streams (peripheral-to-memory or memory-to-peripheral)
• Three peripheral data streams and one memory-to-memory data stream.
The four data streams use a fixed-priority arbitration scheme and share one common
16-word-deep FIFO for buffering burst data. Each of the four data streams has its own
independent set of DMA Registers and address/transfer count counters. In addition:
• Stream2 provides a set of external signals for initiating and controlling DMA transfers
between external peripherals and memory. These signals (DREQ and DACK) are
brought out to external pins that are multiplexed with other functions.
• Stream3 can carry out memory-to-memory DMA transfers under software control.
The DMA Registers are programmed through an APB Slave interface that has a 16-bit
data interface. Therefore, 32-bit registers are accessed as two 16-bit registers: a low 16-
bit half and a high 16-bit half. See Table 12-1 for more information.
The four data streams share a common 16-word-deep FIFO for buffering DMA data. A
stream can be programmed to transfer a number of data units (from 1 to 65535). A data unit
represents a group of bits equal in width to the data width of the source peripheral or mem-
ory. The source and destination data widths can be programmed independently to be byte,
half-word, or word. Data is transferred in bursts, with the burst length programmable to 1, 4,
8, or 16 peripheral data units. The stream has source and destination address registers that
can be independently programmed to remain fixed or increment after each data access.
12-2
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03
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