STMicroelectronics STM32WLEx Reference Manual page 1279

RM0461
36.10.9 TPIU claim tag clear register (TPIU_CLAIMCLR)
Address offset: 0xFA4
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CLAIMCLR[3:0]: resets claim tag bits
Write:
0000: No effect
xxx1: Clears bit 0.
xx1x: Clears bit 1.
x1xx: Clears bit 2.
1xxx: Clears bit 3.
Read: Returns current value of claim tag.
36.10.10 TPIU device configuration register (TPIU_DEVIDR)
Address offset: 0xFC8
Reset value: 0x0000 0CA0
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 SWONRZ: indicates whether serial-wire output, NRZ, is supported
1: Supported
Bit 10 SWOMAN: indicates whether serial-wire output, Manchester encoded format, is supported
1: Supported
Bit 9 TCLKDATA: indicates whether trace clock plus data is supported
0: Supported
27 26 25 24
Res. Res. Res. Res.
11 10 9
Res. Res. Res. Res.
27 26 25 24
Res. Res. Res. Res.
11 10 9
SWON SWOM TCLKD
RZ AN ATA
r r r
RM0461 Rev 5
23 22 21
Res. Res. Res.
8 7 6 5
Res. Res. Res.
23 22 21
Res. Res. Res.
8 7 6 5
CLKRE
FIFOSIZE[2:0]
LAT
r r r r
Debug support (DBG)
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. CLAIMCLR[3:0]
rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
MAXNUM[4:0]
r r r r
16
Res.
0
rw
16
Res.
0
r
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