Table 257. Ap Register Map And Reset Values - STMicroelectronics STM32WLEx Reference Manual

RM0461
36.5.6 AP identification register (AP_IDR)
Address offset: 0xFC
Reset value: 0x2477 0011
31 30 29
REVISION[3:0]
r r r
15 14 13
Res. Res. Res. Res.
Bits 31:28 REVISION[3:0]: revision
0x2: Cortex-M4 r0p3
Bits 27:24 JEDECBANK[3:0]: JEDEC bank
0x4: Arm
Bits 23:17 JEDECCODE[6:0]: JEDEC code
0x3B: Arm
Bit 16 MEMAP: memory access port
0x1: Standard register map
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IDENTITY[7:0]: AP type
0x11: CPU (Cortex-M4) AHB-AP (AP0)
Others: reserved
36.5.7 AP register map and reset values
These registers are not on the CPU memory bus and are only accessed through SW-DP
and JTAG-DP debug interface.
The access port address is 8-bit wide, defined by debug port register
DP_SELECTR.APBANKSEL[3:0] field and by JTAG-DP register DPACC or SW-DP packet
request A[3:2] field.
Offset Register name
AP_CSWR
0x00
Reset value
AP_TAR
0x04
Reset value
0x08 Reserved
AP_DRWR
0x0C
Reset value
28 27 26 25
JEDECBANK[3:0]
r r r r
12 11 10 9
Res. Res. Res.

Table 257. AP register map and reset values

PROT[4:0]
0 0 0 0 1 1 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
24 23 22
r r r
8 7 6
Res.
r r
TA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
TD[31:0]
0 0 0 0 0 0 0 0 0
RM0461 Rev 5
Debug support (DBG)
21 20 19 18
JEDECCODE[6:0]
r r r r
5 4 3 2
IDENTITY[7:0]
r r r r
MODE[3:0]
0 0 0 0 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
17 16
MEMA
P
r r
1 0
r r
0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
1237/1306
1291