STMicroelectronics STM32WLEx Reference Manual page 1238

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
Offset Register name
AP_BD0R
0x10
Reset value
AP_BD1R
0x14
Reset value
AP_BD2R
0x18
Reset value
AP_BD3R
0x1C
Reset value
0x20 to
Reserved
0xF4
AP_BASER
0xF8
Reset value
AP_IDR
0xFC
Reset value
36.6
Data watchpoint and trace unit (DWT)
The DWT provides four comparators that can be used as one of the following function:
watchpoint
PC sampling trigger
data address sampling trigger
data comparator (comparator 1 only)
clock cycle counter comparator (comparator 0 only)
It also contains counters for:
clock cycles
folded instructions
load store unit (LSU) operations
sleep cycles
number of cycles per instruction
interrupt overhead
1238/1306
Table 257. AP register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
TBD[31:0]
0
0
0
0
0
0
0
0
TBD[31:0]
0
0
0
0
0
0
0
0
TBD[31:0]
0
0
0
0
0
0
0
0
TBD[31:0]
0
0
0
0
0
0
0
0
Reserved
BASEADDR[19:0]
0
0
0
1
1
1
1
1
JEDECCODE[6:0]
1
1
1
0
1
1
1
RM0461 Rev 5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
RM0461
0
0
0
0
0 0
0
0
0
0
0 0
0
0
0
0
0 0
0
0
0
0
0 0
0
0
0
0
1 1
IDENTITY[7:0]
0
1
0
0
0 1

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