STMicroelectronics STM32WLEx Reference Manual page 1289

RM0461
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 DBG_TIM2_STOP: TIM2 stop in CPU debug
0: Normal operation. TIM2 continues to operate while CPU is in debug mode.
1: Stop in debug. TIM2 is frozen while CPU is in debug mode.
36.11.4 DBGMCU APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2)
Address offset: 0x044
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DBG_LPTIM3_STOP: LPTIM3 stop in CPU debug
0: Normal operation. LPTIM3 continues to operate while CPU is in debug mode.
1: Stop in debug. LPTIM3 is frozen while CPU is in debug mode.
Bit 5 DBG_LPTIM2_STOP: LPTIM2 stop in CPU debug
0: Normal operation. LPTIM2 continues to operate while CPU is in debug mode.
1: Stop in debug. LPTIM2 is frozen while CPU is in debug mode.
Bits 4:0 Reserved, must be kept at reset value.
36.11.5 DBGMCU APB2 peripheral freeze register
(DBGMCU_APB2FZR)
Address offset: 0x04C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:19 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
DBG_
TIM1 Res. Res.
_STOP
rw
24 23 22
Res. Res. Res.
8 7 6
DBG_ DBG_
Res. Res. LPTIM3 LPTIM2
_STOP _STOP
rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0461 Rev 5
Debug support (DBG)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res.
rw
21 20 19 18
DBG_
Res. Res. Res. TIM17
_STOP
rw
5 4 3 2
Res. Res. Res. Res.
17 16
Res. Res.
1 0
Res. Res.
17 16
DBG_
TIM16 Res.
_STOP
rw
1 0
Res. Res.
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