Table 259. Rom Table - STMicroelectronics STM32WLEx Reference Manual

RM0461
Table 258. DWT register map and reset values (continued)
Offset Register name
DWT_CIDR3
0xFFC
Reset value
Refer to
36.7 ROM table
The ROM table is a CoreSight component that contains the base addresses of all the
CoreSight debug components accessible via the AHB-AP. This table allows a debugger to
discover the topology of the CoreSight system automatically.
There is one ROM table in the CPU sub-system. This table is pointed to by the AP_BASER
register in the CPU AHB-AP. It contains the base address pointer for the system control
space (SCS) registers, which allow the debugger to identify the CPU core, as well as the
FPB, DWT, and CTI
The ROM table (see
from 0xE00FF000 to 0xE00FFFFC.
Address
in ROM table
0xE00FF000
0xE00FF004
0xE00FF008
0xE00FF00C
0xE00FF010
0xE00FF014
0xE00FF018
0xE00FF01C to
0xE00FFFC8
0xE00FFFCC to
0xE00FFFFC
1. CTI is visible in the ROM table but has no function.
The topology for the CoreSight components in the CPU subsystem is shown in
a. CTI is visible in the ROM table but has no function.
Section 36.7: ROM table
(a)
.
Table 259) occupies a 4-Kbyte, 32-bit wide chunk of address space,
Component
name
SCS
DWT
FPB
ITM
TPIU
(1)
CTI
Top of table
Reserved
ROM
table registers
for the register boundary addresses.

Table 259. ROM table

Component Component
base address address offset
0xE000E000 0xFFF0F000
0xE0001000 0xFFF02000
0xE0002000 0xFFF03000
0xE0000000 0xFFF01000
0xE0040000 0xFFF41000
0xE0043000 0xFFF44000
-
-
-
RM0461 Rev 5
Debug support (DBG)
PREAMBLE[27:20]
1 0 1
Size
(bytes)
4 K 0xFFF0F003
4 K 0xFFF02003
4 K 0xFFF03003
4 K 0xFFF01003
4 K 0xFFF41003
4 K 0xFFF44003
- - 0x00000000
- - 0x00000000
- - See
1 0 0 0 1
Entry
Table 259
Figure 374.
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