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RM0461
Bit 5 EMITRANGE: Enables generation of data trace address offset packets (containing data
address bits 0 to 15).
0x0: Disabled
0x1: Enabled
Bit 4 Reserved, must be kept at reset value.
Bits 3:0 FUNCTION[3:0]: Selection of action to take on comparator match
The meaning of this bit field depends on the setting of the DATAVMATCH and CYCMATCH
fields. See [5].
36.6.12
DWT CoreSight peripheral identity register 4 (DWT_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0004
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 F4KCOUNT[3:0]: register file size
0x0: Register file occupies a single 4-Kbyte region.
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x4: Arm
36.6.13
DWT CoreSight peripheral identity register 0 (DWT_PIDR0)
Address offset: 0xFE0
Reset value: 0x0000 0002
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PARTNUM[7:0]: part number bits [7:0]
0x02: DWT part number
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
®
JEDEC code
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
F4KCOUNT[3:0]
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
r
r
RM0461 Rev 5
Debug support (DBG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
JEP106CON[3:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PARTNUM[7:0]
r
r
r
r
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
1245/1306
1291
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