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Debug support (DBG)
36.6.5
DWT sleep count register (DWT_SLPCNTR)
Address offset: 0x010
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 SLEEPCNT[7:0]: sleep cycle counter
Counts the number of cycles spent in sleep mode (WFI, WFE, sleep-on-exit).
36.6.6
DWT LSU count register (DWT_LSUCNTR)
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 LSUCNT[7:0]: load store counter
Counts additional cycles required to execute load and store instructions.
36.6.7
DWT fold count register (DWT_FOLDCNTR)
Address offset: 0x018
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 FOLDCNT[7:0]: folded instruction counter
Increments on each instruction that takes 0 cycles.
1242/1306
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
Res.
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
Res.
rw
rw
RM0461 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
SLEEPCNT[7:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
LSUCNT[7:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
FOLDCNT[7:0]
rw
rw
rw
rw
RM0461
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
rw
rw
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