Figure 375. Tpiu Architecture - STMicroelectronics STM32WLEx Reference Manual

Debug support (DBG)
Offset Register name
ITM_PIDR2
0xFE8
Reset value
ITM_PIDR3
0xFEC
Reset value
ITM_CIDR0
0xFF0
Reset value
ITM_CIDR1
0xFF4
Reset value
ITM_CIDR2
0xFF8
Reset value
ITM_CIDR3
0xFFC
Reset value
Refer to
36.10 Trace port interface unit (TPIU)
The TPIU formats the trace stream and outputs it on the external trace port signals. The
TPIU has one ATB slave ports for incoming trace data from the ITM. The trace port is the
serial-wire output, TRACESWO.
Figure 375
ITM ATB
For more information on the TPIU, refer to the Arm
Reference Manual [2.].
1274/1306
Table 262. ITM register map and reset values (continued)
Section 36.7: ROM table
shows the TPIU architecture.

Figure 375. TPIU architecture

ATB
interface
APB
PPB
interface
for the register boundary addresses.
TPIU
Trace
Formatter output
(serializer)
®
CoreSight™ SoC-400 Technical
RM0461 Rev 5
RM0461
REVISION JEP106ID
[3:0] [6:4]
0 0 1 1 1 0
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1
PREAMBLE
CLASS[3:0]
[11:8]
1 1 1 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1
PREAMBLE[27:20]
1 0 1 1 0 0
TRACESWO
MSv60741V1
1 1
0 0
0 1
0 0
0 1
0 1