Topology 2: Asynchronous Gtl+ Signals Driven By Intel; Ich2; Figure 35. Routing Illustration For Prochot# And Thermtrip# (Topology 1B); Figure 36. Routing Illustration For A20M#, Ignne#, Lint[1:0], Slp#, Smi#, And - Intel Pentium 4 Design Manual

R

Table 15. Layout Recommendations for PROCHOT# and THERMTRIP# Signals (Topology 1b)

Trace Zo
60 Ω

Figure 35. Routing Illustration for PROCHOT# and THERMTRIP# (Topology 1B)

Processor
5.4.1.2

Topology 2: Asynchronous GTL+ Signals Driven by Intel

These signals (A20M#, IGNNE#, LINT[1:0], SLP#, SMI#, and STPCLK#) should adhere to the
following routing and layout recommendations. Figure 36 illustrates the recommended topology.

Table 16. Layout Recommendations for Miscellaneous Signals (Topology 2)

Trace Zo
60 Ω
Figure 36. Routing Illustration for A20M#, IGNNE#, LINT[1:0], SLP#, SMI#, and STPCLK#
® ®
Intel Pentium 4 Processor / Intel
Trace Spacing L1
7 mil 1–17"
Voltage
Translator
L1
Trace Spacing
7 mil 12 inches max
Processor
®
850 Chipset Family Platform Design Guide
L2 L3
10" max 3" max
L2
VDD CPU
R
L3
L1 Rpu
None

ICH2

L1
Topo2_Route
System Bus Routing
Rpu
62 Ω ±5%
External Logic
PU
Topo1b_PROCHOT_Route
®
ICH2
73