Figure 2. Recommended Board Stack-Up Dimensions - Intel 852GM Design Manual

General Design Considerations

Figure 2. Recommended Board Stack-Up Dimensions

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Internal signal traces on Layer 3 and Layer 6 are unbalanced strip-lines. To meet the nominal 55-Ω
characteristic impedance for these traces, they reference a solid ground plane on Layer 2 and Layer 7.
Since the coupling to Layer 4 and Layer 5 is still significant, (especially true when thinner stack-ups use
balanced strip-lines on internal layers) these layers are converted to ground floods in the areas of the
motherboard where the speed critical interfaces like the FSB or DDR system memory are routed. In the
remaining sections of the motherboard layout the Layer 4 and Layer 5 layers are used for power
delivery.
The secondary side layer (L8) is also used for power delivery in many cases, since it benefits from the
thick copper plating of the external layer plating as well as referencing the close Layer 7 ground plane.
The benefit of such a stack-up is low inductance power delivery.
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Dielectric
Stackup Thickness
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PREPREG
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CORE
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PREPREG
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CORE
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PREPREG
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CORE
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PREPREG
Layer Layer
No. Type
(mils)
1 SIGNAL
5.0
2 PLANE
5.0
3 SIGNAL
12.0
4 PLANE
10.0
5 PLANE
12.0
6 SIGNAL
5.0
7 PLANE
5.0
8 SIGNAL
®
Intel 852GM Chipset Platform Design Guide
Copper Trace Trace
Weight Width Impedance
(oz) (mils) (ohms)
1/2+plating 5.0 55
1
1 4.0 55
1
1
4.0 55
1
1
5.0 55
1/2+plating
R