Iec 61850 Edition 1 / Edition 2 Mapping - ABB Relion 650 Series Technical Manual

Section 1
Introduction
1.5
34
Timer tPP=On
STZMPP
BLOCFUNC
Timer tPE=On
STZMPE
BLKTR
BLK
STL1
STL2
STL3
IEC09000887 V3 EN-US
Figure 4: Logic diagram example with a parameter input
Illustrations are used as an example and might show other products
than the one the manual describes. The example that is illustrated is
still valid.

IEC 61850 edition 1 / edition 2 mapping

Function block names are used in ACT and PST to identify functions. Respective
function block names of Edition 1 logical nodes and Edition 2 logical nodes are
shown in the table below.
Table 1: IEC 61850 edition 1 / edition 2 mapping
Function block name
AGSAL
ALMCALH
ALTIM
ALTMS
ALTRK
Table continues on next page
tPP
AND
t
OR
tPE
t
AND
AND
OR
AND
AND
AND
Edition 1 logical nodes
AGSAL
SECLLN0
ALMCALH
-
-
-
1MRK 511 424-UEN B
AND
OR
AND
15ms
TRIP
t
TRL1
TRL2
TRL3
IEC09000887-3-en.vsdx
GUID-C5133366-7260-4C47-A975-7DBAB3A33A96 v6
Edition 2 logical nodes
AGSAL
ALMCALH
ALTIM
ALTMS
ALTRK
Bay control REC650 2.2 IEC
Technical manual