Dead Line Detection - ABB Relion 650 Series Technical Manual

1MRK 511 424-UEN B
7.2.7.3
Bay control REC650 2.2 IEC
Technical manual
20 ms 20 ms
DeltaIL1
t t
20 ms 20 ms
DeltaIL2
t t
20 ms 20 ms
DeltaIL3
t t
20 ms
DeltaUL1
t
20 ms
DeltaUL2
t
20 ms
DeltaUL3
t
IEC12000165 V1 EN-US
Figure 50: Internal signals DeltaU or DeltaI and the corresponding output
signals

Dead line detection

A simplified diagram for the functionality is found in figure 51. A dead phase
condition is indicated if both the voltage and the current in one phase is below their
respective setting values UDLD< and IDLD<. If at least one phase is considered to
be dead the output DLD1PH and the internal signal DeadLineDet1Ph is activated.
If all three phases are considered to be dead the output DLD3PH is activated
Secondary system supervision
intBlock
AND
STDIL1
AND
OR
STDIL2
AND
STDIL3
AND
STDU
AND
STDUL1
AND
OR OR
STDUL2
AND
STDUL3
AND
IEC12000165-1-en.vsd
Section 7
STDI
M13679-44 v4
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