Technical Data - ABB Relion 650 Series Technical Manual

1MRK 511 424-UEN B
9.7.3.3
9.7.4
9.7.4.1
9.7.4.2
9.7.4.3
Bay control REC650 2.2 IEC
Technical manual

Technical data

Table 176: Number of INV instances
Logic block
3 ms
INV 90
Loop delay function block LLD
The Logic loop delay function block (LLD) function is used to delay the output
signal one execution cycle, that is, the cycle time of the function blocks used.
Function block
LLD
INPUT OUT
IEC15000144.vsd
IEC15000144 V1 EN-US
Figure 141: LLD function block
Signals
Table 177: LLD Input signals
Name Type
INPUT BOOLEAN
Table 178: LLD Output signals
Name Type
OUT BOOLEAN
Technical data
Table 179: Number of LLD instances
Logic block
3 ms
LLD 10
Quantity with cycle time
8 ms
90
Default Description
0 Input signal
Description
Output signal delayed one execution cycle
Quantity with cycle time
8 ms
10
Section 9
Logic
GUID-0EC4192A-EF03-47C0-AEC1-09B68B411A98 v3
100 ms
240
GUID-05D959B5-A55B-437C-8E8F-831A4A357E24 v2
GUID-64B24094-010D-4B8F-8B7B-DDD49499AAE5 v3
GUID-EE44CFDF-C8F7-4870-BD1C-98D9CD91FD97 v4
PID-3805-INPUTSIGNALS v5
PID-3805-OUTPUTSIGNALS v5
GUID-B2E6F510-8766-4381-9618-CE02ED71FFB6 v2
100 ms
20
303