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14.6.1
Operation of 16-bit free-run timer
The 16-bit free-run timer starts counting up from counter value specified in timer data
register (TCDT) after a reset has been completed. The counter value is used as the
reference time for 16-bit output compare and 16-bit input capture.
■ Timer Clear
The counter value of 16-bit free-run timer is cleared in the following conditions:
• When a match with compare clear register is detected in up-count mode (TCCSL:MODE=0)
• When "1" is written to the SCLR bit of the TCCSL register during operation. The timer will be cleared
at the valid edge of count clock.
Note:
If writing "0" to the SCLR bit before a valid edge of count clock, the SCLR bit is cleared and the timer
would not be cleared to "0000
• When "0000
• Reset
By a reset, the counter is immediately cleared. By a software clear or a match with compare clear register,
the counter is cleared in synchronization with the count timing. If the
φ
Compare
register value
Compare match
TCCS : SCLR
Counter value
".
H
" is written to the TCDT register during stop.
H
Figure 14.6-1 16-bit Free-run Timer Clear Timing
N -1
N
0000
CHAPTER 14 MULTI-FUNCTIONAL TIMER
N
cleared by hardward
writing "1"
0001
0000
writing "1"
writing "0"
0001
0002
325
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