Figure 3.8.5A Ready Operation; Figure 3.8.5B Ready Signal Generator - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.8 Memory Access Modes
3.8.5 Ready Operation
In external bus mode, the bus cycle can be extended by using the ready operation to
access to the low-speed external memory or peripheral functions.
n Ready Operation
• Externally inputting an "L" level to the ready (RDY) pin operates the ready function.
• If the RDY pin goes to the "L" level when the CPU is performing external access, the latter
half of the bus cycle is extended in CPU operating clock cycle increments (CLK: divide-by-
two source oscillation).
• As the CPU reads the RDY pin state on the rising edge of the CLK signal, the RDY pin must
be established at the "L" level before this timing.
• The CPU wakes up from the ready operation by externally setting the RDY pin to the "H"
level and the bus cycle is complete.
• The CPU ignores the RDY pin state when accessing to an internal area (internal access).
• Pull-up the RDY pin if not using the ready function in external bus mode.
Figure 3.8.5a shows the ready operation.
n Example Ready Input Circuit
84
CHAPTER 3 CPU
CLK
RDY
ALE
A08
to A15
AD0
Lower
to AD7
address
WR

Figure 3.8.5a Ready Operation

MB89620 series
8
AD0 to AD7
ALE
A08 to A15
RDY
CLK

Figure 3.8.5b Ready Signal Generator

Upper address
Write data
Extended cycle
Extended bus cycle
Chip select signal for the low-speed
external memory or peripheral function
D Q
Address latch
AD0 to AD7
G
Address
decoder
8
A08 to A15
Shift register
"H" level
A
B
C
D
E
F
CS
G
H
S/L
Q
H
CLK
MB89620 series