Timer Control Register (8Tcr) - Hitachi H8/3062 Hardware Manual

9.2.4

Timer Control Register (8TCR)

Bit 7
CMIEB
Initial value 0
Read/Write R/W
8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT
clearing specification, and enables interrupt requests.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 9.4, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB Description
0 CMIB interrupt requested by CMFB is disabled
1 CMIB interrupt requested by CMFB is enabled
Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA Description
0 CMIA interrupt requested by CMFA is disabled
1 CMIA interrupt requested by CMFA is enabled
Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt request
when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE Description
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
6 5
CMIEA OVIE CCLR1
0 0
R/W R/W
4 3
CCLR0 CKS2
0 0
R/W R/W R/W
2 1 0
CKS1 CKS0
0 0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
293