Breq Pin Input Timing; Figure 6.24 Brcr Write Timing - Hitachi H8/3062 Hardware Manual

φ
Address bus
PA to PA
7
( A to A
23

BREQ Pin Input Timing

6.7.2
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
4
High-impedance
)
20

Figure 6.24 BRCR Write Timing

T T
1 2
BRCR address
T
3
163