Table 8.7 (A) 16-Bit Timer Operating Modes (Channel 0) - Hitachi H8/3062 Hardware Manual

16-bit timer Operating Modes

Table 8.7 (a) 16-bit timer Operating Modes (Channel 0)

TSNC
Synchro-
Operating Mode nization
Synchronous preset SYNC0 = 1 —
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn- SYNC0 = 1 —
chronous
clear
Legend: Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
Register Settings
TMDR
MDF FDIR PWM
—
— — PWM0 = 1
— — PWM0 = 0
— —
— — PWM0 = 0
— — PWM0 = 0
— —
— —
—
TIOR0
IOA IOB
*
—
IOA2 = 0
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
IOB2 = 1
Other bits
unrestricted
16TCR0
Clear Clock
Select Select
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
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