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22.7.3
Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 22.23 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 22.24 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 22.25 shows the timing of the external three-state access cycle with one wait state
inserted.
• Bus-release mode timing
Figure 22.26 shows the bus-release mode timing.
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