Module Standby Control Register L (Mstcrl) - Hitachi H8/3062 Hardware Manual

Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Reserved: This bit can be written and read.
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1 Description
0 SCI1 operates normally
1 SCI1 is in standby state
Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.
Bit 0
MSTPH0 Description
0 SCI0 operates normally
1 SCI0 is in standby state
21.2.3

Module Standby Control Register L (MSTCRL)

MSTCRL is an 8-bit readable/writable register that controls the module standby function, which
places individual on-chip supporting modules in the standby state. Module standby can be
designated for 16-bit timer, 8-bit timer, and A/D converter modules.
Bit
—
Initial value
Read/Write R/W
MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
640
7 6 5
— —
0 0 0
R/W R/W
Reserved bits
4 3
MSTPL4 MSTPL3 MSTPL2
0 0
R/W R/W
Module standby L4 to L2, L0
These bits select modules to be
placed in standby
(Initial value)
(Initial value)
2 1
— MSTPL0
0 0
R/W R/W R/W
0
0