Table 20.3 (1) Clock Timing For On-Chip Flash Memory Versions; Table 20.3 (2) Clock Timing For On-Chip Mask Rom Versions - Hitachi H8/3062 Hardware Manual

Table 20.3 (1) Clock Timing for On-Chip Flash Memory Versions

Item
External clock input low
pulse width
External clock input high t
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
includes a RES pulse width (t
Note: * t
DEXT

Table 20.3 (2) Clock Timing for On-Chip Mask ROM Versions

Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise
time
External clock fall
time
Clock low pulse
width
Clock high pulse
width
External clock output
settling delay time
includes the RES pulse width (t
Note: * t
DEXT
V = 3.0 V
CC
to 5.5 V
Symbol Min Max
t 30 —
EXL
30 —
30 —
EXH
30 —
t — 8
EXr
t — 8
EXf
t 0.4 0.6
CL
80 —
t 0.4 0.6
CH
80 —
*
t 500 —
DEXT
RESW
V = 2.7 V
CC
to 5.5 V
Symbol Min Max
t 40 —
EXL
40 —
t 40 —
EXH
40 —
t — 10
EXr
t — 10
EXf
t 0.4 0.6
CL
80 —
t 0.4 0.6
CH
80 —
*
t 500 —
DEXT
V = 5.0 V
CC
± 10%
Min Max
t / 2 - 5 —
cyc
55 —
t / 2 - 5 —
cyc
55 —
— 5
— 5
0.4 0.6
80 —
0.4 0.6
80 —
500 —
). t = 20 t
RESW cyc
V = 3.0 V V = 5.0 V
CC CC
to 5.5 V ± 10%
Min Max Min
30 — t / 2 - 5 — ns
cyc
30 — 55
30 — t / 2 - 5 — ns
cyc
30 — 55
— 8 —
— 8 —
0.4 0.6 0.4
80 — 80
0.4 0.6 0.4
80 — 80
500 — 500
). t = 10 t
RESW RESW cyc
Unit Test Conditions
φ > 8 MHz
ns Figure
20.6
φ 8 MHz
ns
φ > 8 MHz
ns
φ 8 MHz
ns
ns
ns
φ ≥ 5 MHz
t
cyc
φ < 5 MHz
ns
φ ≥ 5 MHz
t
cyc
φ < 5 MHz
ns
µs Figure 20.7
MaxUnit Test Conditions
φ > 8 MHz Figure
φ 8 MHz
— ns
φ > 8 MHz
φ 8 MHz
— ns
5 ns
5 ns
φ ≥ 5 MHz
0.6 t
cyc
φ < 5 MHz
— ns
φ ≥ 5 MHz
0.6 t
cyc
φ < 5 MHz
— ns
— µs Figure 20.7
Figure
22.17
20.6
Figure
22.17
631