Figure 8.39 Contention Between 16Tcnt Byte Write And Increment - Hitachi H8/3062 Hardware Manual

Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the
T or T state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not
2 3
incremented. The byte data for which a write was not performed is not incremented, and retains its
pre-write value. See figure 8.39, which shows an increment pulse occurring in the T
byte write to 16TCNTH.
φ
Address bus
Internal write signal
16TCNT input clock
16TCNTH
16TCNTL

Figure 8.39 Contention between 16TCNT Byte Write and Increment

274
16TCNTH byte write cycle
T T
1 2
16TCNTH address
N
16TCNT write data
X X + 1
state of a
2
T
3
M
X