A/D Control Register (Adcr) - Hitachi H8/3062 Hardware Manual

Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS Description
0 Conversion time = 134 states (maximum)
1 Conversion time = 70 states (maximum)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection Channel Selection
CH2 CH1
0 0
1
1 0
1
14.2.3

A/D Control Register (ADCR)

Bit
TRGE
Initial value
Read/Write R/W
Trigger enable
Enables or disables starting of A/D conversion
by an external trigger or 8-bit timer compare match
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by
external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a
reset and in standby mode.
CH0
0
1
0
1
0
1
0
1
7 6 5
— —
0 1 1
— —
Description
Single Mode
AN (Initial value)
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
4 3
— —
1 1
— —
Reserved bits
(Initial value)
Scan Mode
AN
0
AN , AN
0 1
AN to AN
0 2
AN to AN
0 3
AN
4
AN , AN
4 5
AN to AN
4 6
AN to AN
4 7
2 1 0
— — —
1 1 0
— — R/W
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