Hitachi H8/3062 Hardware Manual page 119

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as an interrupt mask bit
1 UI bit in CCR is used as a user bit
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS
in the high-impedance state in software standby mode.
Bit 1
SSOE Description
0 In software standby mode, the address bus and bus control signals are all high-
impedance
1 In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled
to CS , AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed
0 7
(Initial value)
(Initial value)
(Initial value)
(Initial value)
71