Internal Interrupts; Interrupt Exception Handling Vector Table; Figure 5.3 Timing Of Setting Of Irqnf - Hitachi H8/3062 Hardware Manual

Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
input pin
IRQnF
Note: n = 5 to 0
Interrupts IRQ to IRQ
0
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, SCI input/output, or A/D
external trigger input.
5.3.2

Internal Interrupts

27 internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
5.3.3

Interrupt Exception Handling Vector Table

Table 5.3 lists the interrupt exception handling sources, their vector addresses, and their default
priority order. In the default priority order, smaller vector numbers have higher priority. The
priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a
reset is the default order shown in table 5.3.

Figure 5.3 Timing of Setting of IRQnF

have vector numbers 12 to 17. These interrupts are detected regardless of
5
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