Ram Control Register (Ramcr); Table 18.5 Flash Memory Erase Blocks - Hitachi H8/3062 Hardware Manual

Note: Bits 7 to 4 in this register are read-only. These bits must not be set to 1. If bits 7 to 4 are
set when an EBR1/EBR2 bit is set, EBR1/EBR2 will be initialized to H'00.

Table 18.5 Flash Memory Erase Blocks

Block (Size)
EB0 (4 kbytes)
EB1 (4 kbytes)
EB2 (4 kbytes)
EB3 (4 kbytes)
EB4 (4 kbytes)
EB5 (4 kbytes)
EB6 (4 kbytes)
EB7 (4 kbytes)
EB8 (32 kbytes)
EB9 (64 kbytes)
EB10 (64 kbytes)
EB11 (64 kbytes)
18.3.5

RAM Control Register (RAMCR)

Bit 7
—
Initial value 1
Read/Write R
RAMCR specifies the area of flash memory to be overlapped with part of RAM when emulating
realtime flash memory programming. RAMCR is initialized to H'00 by a reset and in hardware
standby mode. RAMCR settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 18.6. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Addresses
H'000000 to H'000FFF
H'001000 to H'001FFF
H'002000 to H'002FFF
H'003000 to H'003FFF
H'004000 to H'004FFF
H'005000 to H'005FFF
H'006000 to H'006FFF
H'007000 to H'007FFF
H'008000 to H'00FFFF
H'010000 to H'01FFFF
H'020000 to H'02FFFF
H'030000 to H'03FFFF
6 5
— —
1 1
R R
4 3
— RAMS RAM2
1 0
R R/W R/W
2 1
RAM1 RAM0
0 0
R/W R/W
0
0
533