Table of Contents
Advertisement
16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals
for a 16-bit, three-state-access area. In these areas, the upper data bus (D
accesses to even addresses and the lower data bus (D
states can be inserted.
Address bus
Read access
Write access
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
150
T
φ
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
High
D
to D
15
8
D
to D
7
0
(Byte Access to Even Address)
to D
) in accesses to odd addresses. Wait
7
0
Bus cycle
T
1
2
Even external address in area n
Valid
Undetermined data
to D
) is used in
15
8
T
3
Valid
Invalid
Advertisement
Table of Contents
