Figure D.3 Reset During Memory Access (Mode 5); Figure D.4 Reset During Operation (Modes 6 And 7) - Hitachi H8/3062 Hardware Manual

P6 /φ
7
RES
Internal reset
signal
A to A
23 0
AS, RD
(read)
HWR, LWR
(write)
D to D
15 0
(write)
I/O port,
CS to CS
7 1
Modes 6 and 7: Figure D.4 is a timing diagram for the case in which RES goes low during an
operation mode 6 or 7. As soon as RES goes low, all ports are initialized to the input state. Clock
/φ goes to the output state at the next rise of φ after RES goes low.
pin P6
7
P6 /φ
7
RES
Internal reset
signal
I/O port
932
Access to external
memory
T1

Figure D.3 Reset during Memory Access (Mode 5)

Figure D.4 Reset during Operation (Modes 6 and 7)

T2 T3
High impedance
High impedance
High impedance
High impedance