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8TCR0—Timer Control Register 0
8TCR1—Timer Control Register 1
7
Bit
CMIEB
Initial value
0
Read/Write
R/W
Compare match interrupt enable B
0
1
6
5
4
CMIEA
OVIE
CCLR1
0
0
0
R/W
R/W
R/W
Counter clear 1 and 0
0
1
Timer overflow interrupt enable
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
H'FFF80
H'FFF81
3
2
CCLR0
CKS2
CKS1
0
0
R/W
R/W
R/W
Clock select 2 to 0
0
Clock input is disabled
0
Internal clock: counted on rising
1
edge of φ/8
0
Internal clock: counted on rising
0
edge of φ/64
1
Internal clock: counted on rising
1
edge of φ/8192
Channel 0:
Count on 8TCNT1 overflow signal *
Channel 1:
0
0
Count on 8TCNT0 compare match
A *
1
1
External clock: counted on falling edge
0
External clock: counted on rising edge
1
External clock: counted on both
1
rising and falling edges
Notes: * If the clock input of channel 0 is the 8TCNT1
overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no
incrementing clock is generated. Do not use
this setting.
0
Clearing is disabled
1
Cleared by compare match A
0
Cleared by compare match B/input capture B
Cleared by input capture B
1
8-bit timer channel 0
8-bit timer channel 1
1
0
CKS0
0
0
R/W
863
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