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φ
Address bus
RD
HWR
Data bus
(a) Idle cycle not inserted
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1)
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall
(assertion) of CS
may occur simultaneously. Figure 6.20 shows an example of the operation in
n
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared to 0, negation of RD in the first read cycle and assertion of CS
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the RD low output in the previous read cycle and the CS
bus cycle will overlap.
As long as RD and CS
non-insertion of an idle cycle can be specified.
φ
Address bus
RD
CSn
Simultaneous change of RD and
CSn: possibility of mutual overlap
(a) Idle cycle not inserted
158
Bus cycle A Bus cycle B
T
T
T
T
T
1
2
3
1
2
Data collision
Long buffer-off time
do not change simultaneously, or if there is no problem even if they do,
n
Bus cycle A Bus cycle B
T
T
T
T
T
1
2
3
1
2
Figure 6.20 Example of Idle Cycle Operation
Bus cycle A Bus cycle B
T
T
1
2
φ
Address bus
RD
HWR
Data bus
(b) Idle cycle inserted
in the following bus cycle
n
low output in the following
n
Bus cycle A Bus cycle B
T
T
1
2
φ
Address bus
RD
CSn
(b) Idle cycle inserted
T
T
T
T
3
i
1
2
T
T
T
T
3
i
1
2
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