Erase Mode; Erase-Verify Mode - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer h8/3062 series; h8/3062b series; h8/3062f-ztat series; h8/3064f-ztat series

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Erase Mode

When erasing flash memory, the single-block erase flowchart shown in figure 17.12 should be

The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in the flash memory control

section 22.2.6, Flash Memory Characteristics.

To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in

erase block register (EBR) at least (x) µs after setting the SWE bit to 1 in FLMCR. Next, the

watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value

greater than ( z ) ms + (y + α + ß) µs as the WDT overflow period. Preparation for entering erase

mode (erase setup) is performed next by setting the ESU bit in FLMCR. The operating mode is

then switched to erase mode by setting the E bit in FLMCR after the elapse of at least (y) µs. The

time during which the E bit is set is the flash memory erase time. Ensure that the erase time does

not exceed (z) ms.

Note: With flash memory erasing, preprogramming (setting all memory data in the memory to

be erased to all 0) is not necessary before starting the erase procedure.

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the fixed erase time, clear the E bit in FLMCR, then wait for at least ( α ) µs

before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer

setting is also cleared. The operating mode is then switched to erase-verify mode by setting the

EV bit in FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be

made to the addresses to be read. The dummy write should be executed after the elapse of (y) µs

or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at

the latched address is read. Wait at least (ε) µs after the dummy write before performing this read

operation. If the read data has been erased (all 1), a dummy write is performed to the next address,

and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the

erase/erase-verify sequence as before. The maximum number of repetitions of the erase/erase-

verify sequence is indicated by the maximum number of erase operations (N).