Timing Of Setting Of Watchdog Timer Reset Bit (Wrst); Figure 11.7 Timing Of Setting Of Wrst Bit And Internal Reset - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer h8/3062 series; h8/3062b series; h8/3062f-ztat series; h8/3064f-ztat series
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11.3.4

Timing of Setting of Watchdog Timer Reset Bit (WRST)

The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 11.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3062 chip. This internal reset signal clears OVF to 0, but the WRST bit
remains set to 1. The reset routine must therefore clear the WRST bit.
φ
TCNT
Overflow signal
OVF
WDT internal
reset
WRST

Figure 11.7 Timing of Setting of WRST Bit and Internal Reset

H'FF
H'00
359

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