Hitachi H8/3062 Hardware Manual page 25

13.2.4 Serial Control Register (SCR).............................................................................. 428
13.3 Operation ........................................................................................................................... 429
13.3.1 Overview .............................................................................................................. 429
13.3.2 Pin Connections.................................................................................................... 429
13.3.3 Data Format.......................................................................................................... 430
13.3.4 Register Settings................................................................................................... 432
13.3.5 Clock .................................................................................................................... 434
13.3.6 Transmitting and Receiving Data......................................................................... 436
13.4 Usage Notes ....................................................................................................................... 443
Section 14 A/D Converter
14.1 Overview............................................................................................................................ 447
14.1.1 Features ................................................................................................................ 447
14.1.2 Block Diagram...................................................................................................... 448
14.1.3 Pin Configuration ................................................................................................. 449
14.1.4 Register Configuration ......................................................................................... 450
14.2 Register Descriptions......................................................................................................... 450
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 450
14.2.2 A/D Control/Status Register (ADCSR)................................................................ 451
14.2.3 A/D Control Register (ADCR)............................................................................. 453
14.3 CPU Interface .................................................................................................................... 454
14.4 Operation ........................................................................................................................... 456
14.4.1 Single Mode (SCAN = 0) ..................................................................................... 456
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 458
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 460
14.4.4 External Trigger Input Timing ............................................................................. 461
14.5 Interrupts............................................................................................................................ 462
14.6 Usage Notes ....................................................................................................................... 462
Section 15 D/A Converter
15.1 Overview............................................................................................................................ 467
15.1.1 Features ................................................................................................................ 467
15.1.2 Block Diagram...................................................................................................... 468
15.1.3 Pin Configuration ................................................................................................. 469
15.1.4 Register Configuration ......................................................................................... 469
15.2 Register Descriptions......................................................................................................... 470
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 470
15.2.2 D/A Control Register (DACR)............................................................................. 470
15.2.3 D/A Standby Control Register (DASTCR).......................................................... 472
15.3 Operation ........................................................................................................................... 472
15.4 D/A Output Control ........................................................................................................... 474
................................................................................................. 447
................................................................................................. 467
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