Hitachi H8/3062 Hardware Manual page 37

Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs .................................. 307
Figure 9.16 Timing of OVF Setting ...................................................................................... 307
Figure 9.17 Example of Pulse Output.................................................................................... 312
Figure 9.18 Contention between 8TCNT Write and Clear.................................................... 313
Figure 9.19 Contention between 8TCNT Write and Increment ............................................ 314
Figure 9.20 Contention between TCOR Write and Compare Match .................................... 315
Figure 9.21 Contention between TCOR Read and Input Capture ......................................... 316
Figure 9.22 Contention between Counter Clearing by Input Capture and Counter
Increment............................................................................................................ 317
Figure 9.23 Contention between TCOR Write and Input Capture ........................................ 318
Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode 319
Figure 10.1 TPC Block Diagram ........................................................................................... 324
Figure 10.2 TPC Output Operation........................................................................................ 339
Figure 10.3 Timing of Transfer of Next Data Register Contents and Output (Example) ..... 340
Figure 10.4 Setup Procedure for Normal TPC Output (Example) ........................................ 341
Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output)................................. 342
Figure 10.6 Setup Procedure for Non-Overlapping TPC Output (Example) ........................ 343
Figure 10.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)......................................................................... 344
Figure 10.8 TPC Output Triggering by Input Capture (Example) ........................................ 345
Figure 10.9 Non-Overlapping TPC Output ........................................................................... 346
Figure 10.10 Non-Overlapping Operation and NDR Write Timing........................................ 347
Figure 11.1 WDT Block Diagram ......................................................................................... 350
Figure 11.2 Format of Data Written to TCNT and TCSR ..................................................... 355
Figure 11.3 Format of Data Written to RSTCSR .................................................................. 356
Figure 11.4 Operation in Watchdog Timer Mode ................................................................. 357
Figure 11.5 Interval Timer Operation.................................................................................... 358
Figure 11.6 Timing of Setting of OVF .................................................................................. 358
Figure 11.7 Timing of Setting of WRST Bit and Internal Reset ........................................... 359
Figure 11.8 Contention between TCNT Write and Count up................................................ 360
Figure 12.1 SCI Block Diagram ............................................................................................ 363
Figure 12.2 Data Format in Asynchronous Communication
(Example: 8-Bit Data with Parity and 2 Stop Bits)............................................ 391
Figure 12.3 Phase Relationship between Output Clock and Serial Data (Asynchronous
Mode) ................................................................................................................. 393
Figure 12.4 Sample Flowchart for SCI Initialization ............................................................ 394
Figure 12.5 Sample Flowchart for Transmitting Serial Data ................................................ 395
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit) ......................................................... 396
Figure 12.7 Sample Flowchart for Receiving Serial Data ..................................................... 397
Figure 12.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 400
Figure 12.9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)................................................ 401
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