Table of Contents
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6.2.2
Access State Control Register (ASTCR).............................................................. 127
6.2.3
Wait Control Registers H and L (WCRH, WCRL).............................................. 128
6.2.4
Bus Release Control Register (BRCR) ................................................................ 132
6.2.5
Bus Control Register (BCR) ................................................................................ 133
6.2.6
Chip Select Control Register (CSCR).................................................................. 135
6.2.7
Address Control Register (ADRCR).................................................................... 136
6.3
Operation ........................................................................................................................... 137
6.3.1
Area Division........................................................................................................ 137
6.3.2
Bus Specifications ................................................................................................ 141
6.3.3
Memory Interfaces................................................................................................ 142
6.3.4
Chip Select Signals............................................................................................... 142
6.3.5
Address Output Method ....................................................................................... 143
6.4
Basic Bus Interface............................................................................................................ 145
6.4.1
Overview .............................................................................................................. 145
6.4.2
Data Size and Data Alignment ............................................................................. 145
6.4.3
Valid Strobes ........................................................................................................ 146
6.4.4
Memory Areas...................................................................................................... 147
6.4.5
Basic Bus Control Signal Timing......................................................................... 148
6.4.6
Wait Control ......................................................................................................... 155
6.5
Idle Cycle........................................................................................................................... 157
6.5.1
Operation .............................................................................................................. 157
6.5.2
Pin States in Idle Cycle ........................................................................................ 159
6.6
Bus Arbiter ........................................................................................................................ 159
6.6.1
Operation .............................................................................................................. 160
6.7
Register and Pin Input Timing .......................................................................................... 162
6.7.1
Register Write Timing.......................................................................................... 162
BREQ Pin Input Timing....................................................................................... 163
6.7.2
Section 7
7.1
Overview............................................................................................................................ 165
7.2
Port 1.................................................................................................................................. 169
7.2.1
Overview .............................................................................................................. 169
7.2.2
Register Descriptions............................................................................................ 169
7.3
Port 2.................................................................................................................................. 172
7.3.1
Overview .............................................................................................................. 172
7.3.2
Register Descriptions............................................................................................ 173
7.4
Port 3.................................................................................................................................. 176
7.4.1
Overview .............................................................................................................. 176
7.4.2
Register Descriptions............................................................................................ 176
7.5
Port 4.................................................................................................................................. 178
7.5.1
Overview .............................................................................................................. 178
7.5.2
Register Descriptions............................................................................................ 179
7.6
Port 5.................................................................................................................................. 181
iv
............................................................................................................ 165
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