Table 22.46 Timing Of On-Chip Supporting Modules - Hitachi H8/3062 Hardware Manual

Table 22.46 Timing of On-Chip Supporting Modules

Condition: T = –20°C to +75°C (regular specifications),
a
T = –40°C to 85°C (wide-range specifications)
a
Condition A: V = 5.0 V ± 10%, AV
CC
fmax = 20 MHz
Condition B: V = 5.0 V ± 10%, AV
CC
fmax = 25 Mhz
Module Item
Ports and Output data delay time
TPC
Input data setup time
Input data hold time
16-bit timer Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
8-bit timer Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
SCI Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Receive data setup time
(synchronous)
Receive
data hold
time (syn-
chronous)
734
= 5.0 V ± 10%, V
CC
= 5.0 V ± 10%, V
CC
Symbol
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
Single edge t
TCKWH
Both edges t
TCKWL
t
TOCD
t
TICS
t
TCKS
Single edge t
TCKWH
Both edges t
TCKWL
Asyn- chronous t
Scyc
Syn- chronous
t
SCKr
t
SCKf
t
SCKW
t
TXD
t
RXS
Clock input t
RXH
Clock output
= 4.5 to AV , V
REF CC
= 4.5 to AV , V
REF CC
Condition
A and B
Min Max Unit
— 50 ns
50 — ns
50 — ns
— 50 ns
50 — ns
50 — ns
1.5 — t
2.5 — t
— 50 ns
50 — ns
50 — ns
1.5 — t
2.5 — t
4 — t
6 — t
1.5 — t
1.5 — t
0.4 0.6 t
— 100 ns
100 — ns
100 — ns
0 — ns
= AV = 0 V,
SS SS
= AV = 0 V,
SS SS
Test
Conditions
Figure 22.27
Figure 22.28
Figure 22.29
cyc
cyc
Figure 22.28
Figure 22.29
cyc
cyc
Figure 22.30
cyc
cyc
cyc
cyc
Scyc
Figure 22.31