Hitachi HD64F3062 Manuals

Manuals and User Guides for Hitachi HD64F3062. We have 2 Hitachi HD64F3062 manuals available for free PDF download: Hardware Manual

Hitachi HD64F3062 Hardware Manual (995 pages)

Single-Chip Microcomputer H8/3062 Series; H8/3062B Series; H8/3062F-ZTAT series; H8/3064F-ZTAT series

Brand: Hitachi | Category: Computer Hardware | Size: 4.08 MB

Table of Contents
17
Section 1 Overview

49
- Overview
  49
Tables

50
Section 2 CPU

77
- Overview
  77
  - Features
    77
  - Differences from H8/300 CPU
    78
- CPU Operating Modes
  79
- Address Space
  79
- Figure 2.1 CPU Operating Modes
  79
- Figure 2.2 Memory Map
  79
- Register Configuration
  80
  - Overview
    80
  - Figure 2.3 CPU Registers
    80
  - 2.4.2 General Registers
    81
  - Figure 2.4 Usage of General Registers
    81
  - Figure 2.5 Stack
    81
  - Table 3.2 Registers
    81
  - Control Registers
    82
  - Initial CPU Register Values
    83
- Data Formats
  84
- Instruction Set
  87
- Addressing Modes and Effective Address Calculation
  101
- Processing States
  107
  - Overview
    107
  - Program Execution State
    107
  - Figure 2.11 Processing States
    107
  - Exception-Handling State
    108
  - Figure 2.12 Classification of Exception Sources
    108
  - Table 2.14 Exception Handling Types and Priority
    108
  - Exception Handling Operation
    109
  - Figure 2.13 State Transitions
    109
  - Bus-Released State
    110
  - Reset State
    110
  - Figure 2.14 Stack Structure after Exception Handling
    110
  - Power-Down State
    111
- Basic Operational Timing
  111
Section 3 MCU Operating Modes

115
Section 4 Exception Handling

133
- Overview
  133
  - Exception Handling Types and Priority
    133
  - Exception Handling Operation
    133
  - Table 4.1 Exception Types and Priority
    133
  - Exception Vector Table
    134
  - Figure 4.1 Exception Sources
    134
  - Table 4.2 Exception Vector Table
    135
- Reset
  136
  - Overview
    136
  - Reset Sequence
    136
  - Figure 4.2 Reset Sequence (Modes 1 and 3)
    137
  - Figure 4.3 Reset Sequence (Modes 2 and 4)
    138
  - Interrupts after Reset
    139
  - Figure 4.4 Reset Sequence (Mode 6)
    139
- Interrupts
  140
- Trap Instruction
  140
- Figure 4.5 Interrupt Sources and Number of Interrupts
  140
- Stack Status after Exception Handling
  141
- Figure 4.6 Stack after Completion of Exception Handling
  141
- Notes on Stack Usage
  142
- Figure 4.7 Operation When SP Value Is Odd
  143
Section 5 Interrupt Controller

145
Section 6 Bus Controller

171
Section 7 I/O Ports

213
- Overview
  213
- Table 7.1 Port Functions
  213
- Port 1
  217
  - Overview
    217
  - Register Descriptions
    217
  - Figure 7.1 Port 1 Pin Configuration
    217
  - Table 7.2 Port 1 Registers
    217
- Port 2
  220
  - Overview
    220
  - Figure 7.2 Port 2 Pin Configuration
    220
  - Register Descriptions
    221
  - Table 7.3 Port 2 Registers
    221
  - Table 7.4 Input Pull-Up Transistor States (Port 2)
    223
- Port 3
  224
  - Overview
    224
  - Register Descriptions
    224
  - Figure 7.3 Port 3 Pin Configuration
    224
  - Table 7.5 Port 3 Registers
    224
- Port 4
  226
  - Overview
    226
  - Figure 7.4 Port 4 Pin Configuration
    226
  - Register Descriptions
    227
  - Table 7.6 Port 4 Registers
    227
- Port 5
  229
  - Overview
    229
  - Figure 7.5 Port 5 Pin Configuration
    229
  - Table 7.7 Input Pull-Up Transistor States (Port 4)
    229
  - Register Descriptions
    230
  - Table 7.8 Port 5 Registers
    230
- Port 6
  232
  - Overview
    232
  - Table 7.9 Input Pull-Up Transistor States (Port 5)
    232
  - Register Descriptions
    233
  - Figure 7.6 Port 6 Pin Configuration
    233
  - Table 7.10 Port 6 Registers
    233
  - Table 7.11 Port 6 Pin Functions in Modes 1 to 5
    235
- Port 7
  236
  - Overview
    236
  - Figure 7.7 Port 7 Pin Configuration
    236
  - Register Description
    237
  - Table 7.12 Port 7 Data Register
    237
- Port 8
  238
  - Overview
    238
  - Figure 7.8 Port 8 Pin Configuration
    238
  - Register Descriptions
    239
  - Table 7.13 Port 8 Registers
    239
  - Table 7.14 Port 8 Pin Functions in Modes 1 to 5
    241
  - Table 7.15 Port 8 Pin Functions in Modes 6 and 7
    242
- Port 9
  243
  - Overview
    243
  - Figure 7.9 Port 9 Pin Configuration
    243
  - Register Descriptions
    244
  - Table 7.16 Port 9 Registers
    244
  - Table 7.17 Port 9 Pin Functions
    246
- Port a
  248
- Port B
  260
  - Overview
    260
  - Figure 7.11 Port B Pin Configuration
    261
  - Register Descriptions
    262
  - Table 7.22 Port B Registers
    262
  - Table 7.23 Port B Pin Functions (Modes 1 to 5)
    264
  - Table 7.24 Port B Pin Functions (Modes 6 and 7)
    266
Section 8 16-Bit Timer

269
8-Bit Timers

333
Section 10 Programmable Timing Pattern Controller (TPC)

371
- Overview
  371
  - Features
    371
  - Block Diagram
    372
  - Figure 10.1 TPC Block Diagram
    372
  - Pin Configuration
    373
  - Table 10.1 TPC Pins
    373
  - Register Configuration
    374
  - Table 10.2 TPC Registers
    374
- Register Descriptions
  375
  - Port a Data Direction Register (PADDR)
    375
  - Port a Data Register (PADR)
    375
  - Port B Data Direction Register (PBDDR)
    376
  - Port B Data Register (PBDR)
    376
  - Next Data Register a (NDRA)
    377
  - Next Data Register B (NDRB)
    379
  - Next Data Enable Register a (NDERA)
    381
  - Next Data Enable Register B (NDERB)
    382
  - TPC Output Control Register (TPCR)
    383
  - TPC Output Mode Register (TPMR)
    385
- Operation
  387
- Usage Notes
  394
Section 11 Watchdog Timer

397
- Overview
  397
  - Features
    397
  - Block Diagram
    398
  - Pin Configuration
    398
  - Figure 11.1 WDT Block Diagram
    398
  - Table 11.1 WDT Pin
    398
  - Register Configuration
    399
- Register Descriptions
  399
- Operation
  405
- Interrupts
  408
- Usage Notes
  408
- Figure 11.8 Contention between TCNT Write and Count up
  408
Section 12 Serial Communication Interface

409
Section 13 Smart Card Interface

469

Hitachi HD64F3062 Hardware Manual (939 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.98 MB

Table of Contents
11
Section 1 Overview

26
Cpu

52
- Overview
  52
  - Features
    52
  - Differences from H8/300 CPU
    53
- CPU Operating Modes
  53
- Address Space
  54
- Register Configuration
  55
  - Overview
    55
  - 2.4.2 General Registers
    56
  - Control Registers
    57
  - Initial CPU Register Values
    58
- Data Formats
  59
  - General Register Data Formats
    59
  - Memory Data Formats
    60
- Instruction Set
  62
- Addressing Modes and Effective Address Calculation
  76
  - Addressing Modes
    76
  - Effective Address Calculation
    78
- Processing States
  82
  - Overview
    82
  - Program Execution State
    82
  - Exception-Handling State
    83
  - Exception Handling Operation
    84
  - Bus-Released State
    85
  - Reset State
    85
  - Power-Down State
    86
- Basic Operational Timing
  86
MCU Operating Modes

89
- Overview
  89
  - Operating Mode Selection
    89
  - Register Configuration
    90
- Mode Control Register (MDCR)
  90
- System Control Register (SYSCR)
  91
- Operating Mode Descriptions
  93
  - Mode 1
    93
  - Mode 2
    93
  - Mode 3
    94
  - Mode 4
    94
  - Mode 5
    94
  - Mode 7
    94
- Pin Functions in each Operating Mode
  95
- Memory Map in each Operating Mode
  96
  - Comparison of H8/3062 Series Memory Maps
    96
  - Reserved Areas
    97
Exception Handling

106
- Overview
  106
  - Exception Handling Types and Priority
    106
  - Exception Handling Operation
    106
  - Exception Vector Table
    107
- Reset
  109
  - Reset Sequence
    109
  - Interrupts after Reset
    112
- Interrupts
  113
- Trap Instruction
  113
- Stack Status after Exception Handling
  114
- Notes on Stack Usage
  115
  - Overview
    117
Interrupt Controller

117
- Features
  117
- Block Diagram
  118
- Pin Configuration
  119
- Register Configuration
  119
- Register Descriptions
  119
- Interrupt Sources
  128
  - External Interrupts
    128
  - Internal Interrupts
    129
  - Interrupt Exception Handling Vector Table
    129
- Interrupt Operation
  133
  - Interrupt Handling Process
    133
  - Interrupt Exception Handling Sequence
    138
  - Interrupt Response Time
    139
- Usage Notes
  140
Bus Controller

142
- Overview
  142
  - Features
    142
  - Block Diagram
    143
  - Pin Configuration
    144
  - Register Configuration
    145
- Register Descriptions
  145
- Operation
  156
  - Area Division
    156
  - Bus Specifications
    159
  - Memory Interfaces
    160
  - Address Output Method
    161
- Basic Bus Interface
  163
  - Overview
    163
  - Data Size and Data Alignment
    163
  - Valid Strobes
    164
  - Memory Areas
    165
  - Basic Bus Control Signal Timing
    166
  - Wait Control
    173
- Idle Cycle
  175
  - Operation
    175
  - Pin States in Idle Cycle
    177
- Bus Arbiter
  177
  - Operation
    178
- Register and Pin Input Timing
  180
  - Register Write Timing
    180
  - BREQ Pin Input Timing
    181
I/O Ports

182
- Overview
  182
- Port 1
  186
  - Overview
    186
  - Register Descriptions
    186
- Port 2
  189
  - Overview
    189
  - Register Descriptions
    190
- Port 3
  193
  - Overview
    195
  - Register Descriptions
    199
- Port 4
  201
  - Overview
    201
- Port 5
  201
  - Overview
    205
- Port 6
  205
- Port 7
  205
  - Register Description
    206
- Port 8
  207
  - Overview
    207
  - Register Descriptions
    213
  - Overview
    217
- Port a
  217
  - Register Descriptions
    219
- Port B
  229
  - Overview
    229
  - Register Descriptions
    231
16-Bit Timer

237
- Overview
  237
  - Features
    237
  - Block Diagrams
    239
  - Pin Configuration
    242
  - Register Configuration
    243
- Register Descriptions
  244
- CPU Interface
  264
  - 16-Bit Accessible Registers
    264
  - 8-Bit Accessible Registers
    266
- Operation
  267
  - Overview
    267
  - Basic Functions
    267
  - Synchronization
    275
  - PWM Mode
    277
  - Phase Counting Mode
    281
  - 16-Bit Timer Output Timing
    283
- Interrupts
  284
  - Setting of Status Flags
    284
  - Timing of Clearing of Status Flags
    286
  - Usage Notes
    288
8-Bit Timers

300
- Overview
  300
  - Features
    300
  - Block Diagram
    302
  - Pin Configuration
    303
  - Register Configuration
    304
- Register Descriptions
  305
  - Timer Counters (8TCNT)
    305
  - Time Constant Registers a (TCORA)
    306
  - Time Constant Registers B (TCORB)
    307
  - Timer Control Register (8TCR)
    308
  - Timer Control/Status Registers (8TCSR)
    311
- CPU Interface
  316
  - 8-Bit Registers
    316
- Operation
  318
  - 8TCNT Count Timing
    318
  - Compare Match Timing
    319
  - Input Capture Signal Timing
    320
  - Timing of Status Flag Setting
    321
  - Operation with Cascaded Connection
    322
  - Input Capture Setting
    325
- Interrupt
  326
  - Interrupt Sources
    326
  - A/D Converter Activation
    327
- 8-Bit Timer Application Example
  327
- Usage Notes
  328
Section 10 Programmable Timing Pattern Controller (TPC)

338
- Overview
  338
  - Features
    338
  - Block Diagram
    339
  - Pin Configuration
    340
  - Register Configuration
    341
- Register Descriptions
  342
  - Port a Data Direction Register (PADDR)
    342
  - Port a Data Register (PADR)
    342
  - Port B Data Direction Register (PBDDR)
    343
  - Port B Data Register (PBDR)
    343
  - Next Data Register a (NDRA)
    344
  - Next Data Register B (NDRB)
    346
  - Next Data Enable Register a (NDERA)
    348
  - Next Data Enable Register B (NDERB)
    349
  - TPC Output Control Register (TPCR)
    350
  - TPC Output Mode Register (TPMR)
    352
- Operation
  354
  - Overview
    354
  - Output Timing
    355
  - Normal TPC Output
    356
  - Non-Overlapping TPC Output
    358
  - TPC Output Triggering by Input Capture
    360
- Usage Notes
  361
  - Operation of TPC Output Pins
    361
  - Note on Non-Overlapping Output
    361

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Hitachi HD64F3062 Manuals

Hitachi HD64F3062 Hardware Manual (995 pages)

Table of Contents

Section 1 Overview

Tables

Figures

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 I/O Ports

Section 8 16-Bit Timer

8-Bit Timers

Section 10 Programmable Timing Pattern Controller (TPC)

Section 11 Watchdog Timer

Section 12 Serial Communication Interface

Section 13 Smart Card Interface

Hitachi HD64F3062 Hardware Manual (939 pages)

Table of Contents

Section 1 Overview

Cpu

MCU Operating Modes

Exception Handling

Interrupt Controller

Bus Controller

I/O Ports

16-Bit Timer

8-Bit Timers

Section 10 Programmable Timing Pattern Controller (TPC)

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