Figure 6.21 Example Of External Bus Master Operation - Hitachi H8/3062 Hardware Manual

φ
Address bus
Data bus
AS
RD
HWR, LWR
BREQ
BACK

Figure 6.21 Example of External Bus Master Operation

When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
CPU cycles
T T T
0 1 2
Address
High
Minimum 3 cycles
(1) (2)
External bus released
High-impedance
High-impedance
High-impedance
High-impedance
High-impedance
(3) (4) (5)
CPU cycles
(6)
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