Table of Contents
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11.2.4 Notes on Register Rewriting ................................................................................ 355
11.3 Operation ........................................................................................................................... 357
11.3.1 Watchdog Timer Operation.................................................................................. 357
11.3.2 Interval Timer Operation...................................................................................... 358
11.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 358
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 359
11.4 Interrupts............................................................................................................................ 360
11.5 Usage Notes ....................................................................................................................... 360
12.1 Overview............................................................................................................................ 361
12.1.1 Features ................................................................................................................ 361
12.1.2 Block Diagram...................................................................................................... 363
12.1.3 Pin Configuration ................................................................................................. 364
12.1.4 Register Configuration ......................................................................................... 365
12.2 Register Descriptions......................................................................................................... 366
12.2.1 Receive Shift Register (RSR)............................................................................... 366
12.2.2 Receive Data Register (RDR) .............................................................................. 366
12.2.3 Transmit Shift Register (TSR).............................................................................. 367
12.2.4 Transmit Data Register (TDR) ............................................................................. 367
12.2.5 Serial Mode Register (SMR)................................................................................ 368
12.2.6 Serial Control Register (SCR).............................................................................. 371
12.2.7 Serial Status Register (SSR)................................................................................. 375
12.2.8 Bit Rate Register (BRR)....................................................................................... 380
12.3 Operation ........................................................................................................................... 388
12.3.1 Overview .............................................................................................................. 388
12.3.2 Operation in Asynchronous Mode........................................................................ 391
12.3.3 Multiprocessor Communication ........................................................................... 400
12.3.4 Synchronous Operation ........................................................................................ 407
12.4 SCI Interrupts .................................................................................................................... 415
12.5 Usage Notes ....................................................................................................................... 416
12.5.1 Notes on Use of SCI ............................................................................................. 416
13.1 Overview............................................................................................................................ 421
13.1.1 Features ................................................................................................................ 421
13.1.2 Block Diagram...................................................................................................... 422
13.1.3 Pin Configuration ................................................................................................. 422
13.1.4 Register Configuration ......................................................................................... 423
13.2 Register Descriptions......................................................................................................... 424
13.2.1 Smart Card Mode Register (SCMR) .................................................................... 424
13.2.2 Serial Status Register (SSR)................................................................................. 426
13.2.3 Serial Mode Register (SMR)................................................................................ 427
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................................................................ 361
...................................................................................... 421
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