Operation; Watchdog Timer Operation; Figure 11.4 Operation In Watchdog Timer Mode - Hitachi H8/3062 Hardware Manual

11.3

Operation

Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
11.3.1

Watchdog Timer Operation

Figure 11.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3062 is internally reset for a duration of 518 states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR. Note that there is no RESO pin in the versions with on-
chip flash memory.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
H'FF
TCNT count
value
H'00
Internal
reset signal
RESO
Start H'00 written
in TCNT

Figure 11.4 Operation in Watchdog Timer Mode

WDT overflow
TME set to 1
OVF = 1
Reset
518 states
132 states
H'00 written
in TCNT
357