Hitachi H8/3062 Hardware Manual page 23

9.7.6 Contention between TCOR Write and Input Capture .......................................... 318
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection) ........................................................................................ 319
9.7.8 Contention between Compare Matches A and B ................................................. 320
9.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 320
Section 10 Programmable Timing Pattern Controller (TPC)
10.1 Overview............................................................................................................................ 323
10.1.1 Features ................................................................................................................ 323
10.1.2 Block Diagram...................................................................................................... 324
10.1.3 Pin Configuration ................................................................................................. 325
10.1.4 Register Configuration ......................................................................................... 326
10.2 Register Descriptions......................................................................................................... 327
10.2.1 Port A Data Direction Register (PADDR) ........................................................... 327
10.2.2 Port A Data Register (PADR) .............................................................................. 327
10.2.3 Port B Data Direction Register (PBDDR)............................................................ 328
10.2.4 Port B Data Register (PBDR)............................................................................... 328
10.2.5 Next Data Register A (NDRA) ............................................................................ 329
10.2.6 Next Data Register B (NDRB) ............................................................................. 331
10.2.7 Next Data Enable Register A (NDERA).............................................................. 333
10.2.8 Next Data Enable Register B (NDERB) .............................................................. 334
10.2.9 TPC Output Control Register (TPCR) ................................................................. 335
10.2.10 TPC Output Mode Register (TPMR) ................................................................... 337
10.3 Operation ........................................................................................................................... 339
10.3.1 Overview .............................................................................................................. 339
10.3.2 Output Timing ...................................................................................................... 340
10.3.3 Normal TPC Output ............................................................................................. 341
10.3.4 Non-Overlapping TPC Output ............................................................................. 343
10.3.5 TPC Output Triggering by Input Capture ............................................................ 345
10.4 Usage Notes ....................................................................................................................... 346
10.4.1 Operation of TPC Output Pins ............................................................................. 346
10.4.2 Note on Non-Overlapping Output........................................................................ 346
Section 11 Watchdog Timer
11.1 Overview............................................................................................................................ 349
11.1.1 Features ................................................................................................................ 349
11.1.2 Block Diagram...................................................................................................... 350
11.1.3 Pin Configuration ................................................................................................. 350
11.1.4 Register Configuration ......................................................................................... 351
11.2 Register Descriptions......................................................................................................... 351
11.2.1 Timer Counter (TCNT) ........................................................................................ 351
11.2.2 Timer Control/Status Register (TCSR) ................................................................ 352
11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 354
............................................................................................. 349
.................................. 323
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