Contention Between 8Tcnt Byte Write And Increment In 16-Bit Count Mode (Cascaded Connection); Figure 9.24 Contention Between 8Tcnt Byte Write And Increment In 16-Bit Count Mode - Hitachi H8/3062 Hardware Manual

9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T
the counter write takes priority and the byte data for which the write was performed is not
incremented. The byte data for which a write was not performed is incremented. Figure 9.24
shows the timing when an increment pulse occurs in the T
byte). If an increment pulse occurs in the T
Address bus
Internal write signal
8TCNT input clock
8TCNT (upper byte)
8TCNT (lower byte)

Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

state of an 8TCNT byte write cycle in 16-bit count mode,
3
2
8TCNT (upper byte) byte write cycle
T
1
φ
state of a byte write to 8TCNT (upper
2
state, on the other hand, the increment takes priority.
T
2
8TCNTH address
N
X
T
3
N+1 8TCNT write data
X+1
319