Hitachi H8/3062 Hardware Manual page 19

4.1.3 Exception Vector Table........................................................................................ 86
4.2 Reset .................................................................................................................................. 88
4.2.1 Overview .............................................................................................................. 88
4.2.2 Reset Sequence..................................................................................................... 88
4.2.3 Interrupts after Reset ............................................................................................ 91
4.3 Interrupts............................................................................................................................ 92
4.4 Trap Instruction ................................................................................................................. 92
4.5 Stack Status after Exception Handling .............................................................................. 93
4.6 Notes on Stack Usage........................................................................................................ 94
Section 5 Interrupt Controller
5.1 Overview............................................................................................................................ 97
5.1.1 Features ................................................................................................................ 97
5.1.2 Block Diagram...................................................................................................... 98
5.1.3 Pin Configuration ................................................................................................. 99
5.1.4 Register Configuration ......................................................................................... 99
5.2 Register Descriptions......................................................................................................... 99
5.2.1 System Control Register (SYSCR) ...................................................................... 99
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 100
5.2.3 IRQ Status Register (ISR) .................................................................................... 105
5.2.4 IRQ Enable Register (IER) .................................................................................. 106
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 107
5.3 Interrupt Sources................................................................................................................ 108
5.3.1 External Interrupts................................................................................................ 108
5.3.2 Internal Interrupts ................................................................................................. 109
5.3.3 Interrupt Exception Handling Vector Table ......................................................... 109
5.4 Interrupt Operation ............................................................................................................ 113
5.4.1 Interrupt Handling Process ................................................................................... 113
5.4.2 Interrupt Exception Handling Sequence .............................................................. 118
5.4.3 Interrupt Response Time ...................................................................................... 119
5.5 Usage Notes ....................................................................................................................... 120
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 120
5.5.2 Instructions that Inhibit Interrupts........................................................................ 121
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 121
Section 6 Bus Controller
6.1 Overview............................................................................................................................ 123
6.1.1 Features ................................................................................................................ 123
6.1.2 Block Diagram...................................................................................................... 124
6.1.3 Pin Configuration ................................................................................................. 125
6.1.4 Register Configuration ......................................................................................... 126
6.2 Register Descriptions......................................................................................................... 126
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 126
........................................................................................ 97
.................................................................................................. 123
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