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Type
Symbol
Operating
MD
to
2
mode
MD
0
control
RES
System
control
RESO
FWE
STBY
BREQ
BACK
Interrupts NMI
IRQ
to
5
IRQ
0
Address
A
to A
23
0
bus
14
Pin No.
FP-100B
TFP-100B FP-100A I/O
75 to 73
77 to 75 Input
63
65
10
12
10
12
62
64
59
61
60
62
64
66
17, 16,
19, 18,
90 to 87
92 to 89
97 to 100,
99, 100,
56 to 45,
1, 2,
43 to 36
58 to 47,
45 to 38
Name and Function
Mode 2 to mode 0: For setting the operating
mode, as follows. Inputs at these pins must
not be changed during operation.
MD
MD
2
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Input
Reset input: When driven low, this pin resets
the chip. This pin must be driven low at power-
up.
Output Reset output (On-chip mask ROM
versions): Outputs the reset signal generated
by the watchdog timer to external devices.
Input
Write enable signal (On-chip flash memory
versions): Flash memory programming
control signal
Input
Standby: When driven low, this pin forces
a transition to hardware standby mode.
Input
Bus request: Used by an external bus master
to request the bus right.
Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master.
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt.
Input
Interrupt request 5 to 0: Maskable interrupt
request pins
Output Address bus: Output address signals.
MD
Operating Mode
0
0
Setting prohibited
1
Mode 1
0
Mode 2
1
Mode 3
0
Mode 4
1
Mode 5
0
Mode 6
1
Mode 7
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