System Clock Output Disabling Function; Figure 21.3 Starting And Stopping Of System Clock Output; Table 21.4 Φ Pin State In Various Operating States - Hitachi H8/3062 Hardware Manual

21.7

System Clock Output Disabling Function

Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the
PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-
impedance state. Figure 21.3 shows the timing of the stopping and starting of system clock output.
When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 21.4 indicates
the state of the φ pin in various operating states.
MSTCRH write cycle
(PSTOP = 1)
T1
φ pin

Figure 21.3 Starting and Stopping of System Clock Output

Table 21.4 φ φ φ φ Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
T2 T3
High impedance
PSTOP = 0
High impedance
Always high
System clock output
System clock output
MSTCRH write cycle
(PSTOP = 0)
T1 T2 T3
PSTOP = 1
High impedance
High impedance
High impedance
High impedance
649