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9.2.4
Timer Control Register (8TCR)
Bit
CMIEB
Initial value
Read/Write
R/W
8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT
clearing specification, and enables interrupt requests.
8TCR is initialized to H'00 by a reset and in standby mode.
For the timing, see section 9.4, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB
0
1
Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA
0
1
Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt request
when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE
0
1
7
6
CMIEA
OVIE
0
0
R/W
R/W
Description
CMIB interrupt requested by CMFB is disabled
CMIB interrupt requested by CMFB is enabled
Description
CMIA interrupt requested by CMFA is disabled
CMIA interrupt requested by CMFA is enabled
Description
OVI interrupt requested by OVF is disabled
OVI interrupt requested by OVF is enabled
5
4
CCLR1
CCLR0
0
0
R/W
R/W
3
2
CKS2
CKS1
0
0
R/W
R/W
1
0
CKS0
0
0
R/W
(Initial value)
(Initial value)
(Initial value)
243
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