Timer Control/Status Registers (8Tcsr) - Hitachi H8/3062 Hardware Manual

9.2.5

Timer Control/Status Registers (8TCSR)

8TCSR0
Bit 7
CMFB
Initial value 0
Read/Write R/(W)*
8TCSR2
Bit 7
CMFB
Initial value 0
Read/Write R/(W)*
8TCSR1, 8TCSR3
Bit 7
CMFB
Initial value 0
Read/Write R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers 8TCSR are 8-bit registers that indicate compare match/input
capture and overflow statuses, and control compare match output/input capture edge selection.
8TCSR2 is initialized to H'10, and 8TCSR0, 8TCSR1, and 8TCSR3 to H'00, by a reset and in
standby mode.
296
6 5
CMFA OVF
ADTE
0 0
R/(W)* R/(W)*
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
4 3
OIS3 OIS2
0 0
R/W R/W R/W
4 3
— OIS3 OIS2
1 0
— R/W R/W
4 3
ICE OIS3 OIS2
0 0
R/W R/W R/W
2 1 0
OS1 OS0
0 0 0
R/W R/W
2 1 0
OS1 OS0
0 0 0
R/W R/W
2 1 0
OS1 OS0
0 0 0
R/W R/W