Setting when Input Capture Occurs
• The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3
and input capture occurs.
• TMIO
pin input capture input signal edge detection is selected by bits OIS3 and OIS2
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in 8TCSR2.
Counter Clear Specification
• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.
• The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits
cannot be cleared independently.
OVF Flag Operation
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
H'FF to H'00).
Compare Match Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in
channel 0 cannot be used.
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR3, the compare match register function of TCORB2 in
channel 2 cannot be used.
Caution
Do not set 16-bit counter mode and compare match count mode simultaneously within the same
group, as the 8TCNT input clock will not be generated and the counters will not operate.
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