Erase Block Register (Ebr) - Hitachi H8/3062 Hardware Manual

Notes: *1 Do not set multiple bits simultaneously.
Do not cut V
*2 The SWE bit must not be set or cleared at the same time as other bits (ESU, PSU, EV,
PV, E, or P).
*3 P bit and E bit setting should be carried out in accordance with the program/erase
algorithm shown in section 17.5, Flash Memory Programming/Erasing.
See section 17.9, Flash Memory Programming and Erasing Precautions, for more
information on the use of these bits.
17.3.2

Erase Block Register (EBR)

EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode or software standby mode, when a high level is not
input to the FWE pin, or when the SWE bit in FLMCR is 0 when a high level is applied to the
FWE pin. When a bit is set in EBR, the corresponding block can be erased. Other blocks are erase-
protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not set bits
in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR is set. The flash memory block
configuration is shown in table 17.4. To erase all the blocks, erase each block sequentially.
The H8/3062F-ZTAT and the H8/3062F-ZTAT R-mask version do not support the on-board
programming mode in mode 6, so bits in this register cannot be set to 1 in mode 6.
Bit
Initial value
Modes 1
Read/Write
to 4, and 6
Modes 5 Initial value
and 7 Read/Write
Bits 7 to 0—Block 7 to Block 0 (EB7 to EB0): Setting one of these bits specifies the
corresponding block (EB7 to EB0) for erasure.
Bits 7–0
EB7–EB0 Description
0 Corresponding block (EB7 to EB0) not selected
1 Corresponding block (EB7 to EB0) selected
Note: When not performing an erase, clear all EBR bits to 0.
486
when a bit is set.
CC
7 6
EB7 EB6
0 0
R R
0 0
R/W R/W
5 4 3
EB5 EB4 EB3
0 0 0
R R R
0 0 0
R/W R/W R/W
2 1 0
EB2 EB1 EB0
0 0 0
R R R
0 0 0
R/W R/W R/W
(Initial value)